南京师范大学电气与电子工程学院教学授课计划Chp.8DIGITALCIRCUITNOISEANDLAYOUT（数字电路的噪声和布局）本章学习要求：了解如下主要概念、方法和内容。时域与频域关系，模拟与数字电路关系等数字逻辑器件的噪声（内部噪声源分析）数字电路接地系统噪声（接地线电感的影响；减小电感的方法，实际数字电路接地系统考虑等）电源分配（电源解偶解偶电容类型与数值，电解解偶电容，解偶电容的配置）噪声电压控制目标与测量§8.1IntroductionAdigitalsystemisalsoaradio-frequency(RF)systemwithnoiseandinterferencepotentialSmallICdigitallogicgates(数字逻辑门电路),whichdrawonlyafewmAcurrent,canalsobeaseriousnoisesourceforhighswitchingspeedcombinedwithinductanceoftheconductorThenoisesourcewhencurrentchangethroughaninductorExample:“on”state,I=5mA,“off”state,I=1mASo,however!!Alsoifapowersupplywiringhasaninductanceof500mH,L=500mHThenoisevoltageacrossthepowersupplywiringwhengatechangestate=1V!Realizingthepowersupplyvoltageofthissystemisonly5V,thereforeChp.8andChp.9willdiscusstechniquestominimize(1)internalnoisegeneration(2)radiatedemission§8.2FrequencyVersusTimeDomain(频域与时域关系)Thoughdigitalcircuitworksintimedomain,becauselegalrequirementontheemissionarespecifiedinfrequency-domain,so“f”versus“t”shouldbeknownBandwidthofadigitalsystemDefinition:logicpulsebandwidthshouldbethepoint,wheretheenergycontentintheharmonic(consistasquarewave)isnegligiblewhenbeyondthispoint.OrthebreakpointwheretheFouriercoefficientstarttodecayat40dB/decadetr:pulserisetimee.g.tr=2ns,BW=159MHzTypicalrise/falltimeandrelatedbandwidthforlogicdevice§8.3AnalogVersusDigitalCircuitInananalogcircuit,smallnoisecoupledintocircuitmaycauseinterference,whichoftenoccursinlowsignallevel(mV,mA)orinhigh-gainamplifier;Incontrast,digitalcircuithavenoamplifierandoperateatlargesignallevelFornoisemarginLSTTL,VN=400mV~600mV,CMOS,VN=1.5V(Vcc=5V),Sodigitalcircuithaveaninherentimmunitytolow-levelnoise§8.4DigitalLogicNoiseInanalogcircuit,externalnoiseisusuallytheprimaryconcern,however,indigitalcircuit,internalnoisesourceisthemajorconcernReasonforinternalnoisegroundbusnoisepowerbusnoisetransmissionlinereflectioncrosstalkNoisemeasurementrequirementgroundvoltagedifferencebetweenvariouspointsinthesystemVcc