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DM74LS1658-BitParallelIn/SerialOutputShiftRegistersShiftOutputIn/SerialParallel8-BitDM74LS165August1986RevisedMarch2000DM74LS1658-BitParallelIn/SerialOutputShiftRegistersGeneralDescriptionFeaturesThisdeviceisan8-bitserialshiftregisterwhichshiftsdata■ComplementaryoutputsinthedirectionofQAtowardQHwhenclocked.Parallel-in■Directoverriding(data)inputsaccessismadeavailablebyeightindividualdirectdata■Gatedclockinputsinputs,whichareenabledbyalowlevelattheshift/load■Parallel-to-serialdataconversioninput.Theseregistersalsofeaturegatedclockinputsandcomplementaryoutputsfromtheeighthbit.■Typicalfrequency35MHzClockingisaccomplishedthrougha2-inputNORgate,per-■Typicalpowerdissipation105mWmittingoneinputtobeusedasaclock-inhibitfunction.HoldingeitheroftheclockinputsHIGHinhibitsclocking,andholdingeitherclockinputLOWwiththeloadinputHIGHenablestheotherclockinput.Theclock-inhibitinputshouldbechangedtothehighlevelonlywhiletheclockinputisHIGH.ParallelloadingisinhibitedaslongastheloadinputisHIGH.DataattheparallelinputsareloadeddirectlyintotheregisteronaHIGH-to-LOWtransitionoftheshift/loadinput,regardlessofthelogiclevelsontheclock,clockinhibit,orserialinputs.OrderingCode:OrderNumberPackageNumberPackageDescriptionDM74LS165MM16A16-LeadSmallOutlineIntegratedCircuit(SOIC),JEDECMS-012,0.150NarrowDM74LS165WMM16B16-LeadSmallOutlineIntergratedCircuit(SOIC),JEDECMS-013,0.300WideDM74LS165NN16E16-LeadPlasticDual-In-LinePackage(PDIP),JEDECMS-001,0.300WideDevicesalsoavailableinTapeandReel.Specifybyappendingthesuffixletter“X”totheorderingcode.ConnectionDiagramFunctionTableInputsInternalShift/ClockClockSerialParallelOutputsOutputLoadInhibitA...HQAQBQHLXXXa...habhHLLXXQA0QB0QH0↑HLHXHQAnQGn↑HLLXLQAnQGnHHXXXQA0QB0QH0H=HIGHLevel(steadystate)L=LOWLevel(steadystate)X=Don'tCare(anyinput,includingtransitions)↑=TransitionfromLOW-to-HIGHlevela...h=Thelevelofsteady-stateinputatinputsAthroughH,respectively.=QA0,QB0,QH0ThelevelofQA,QB,orQH,respectively,beforetheind