学院计算机组成原理实验报告年级学号姓名成绩专业实验地点指导教师实验项目乘法器实验日期实验目的：理解并掌握乘法器的原理实验步骤打开QuartusII。将子板上的JTAG端口与PC机的并行口用下载电缆连接。打开实验台电源。执行Tools—Programmer命令，将shifter.sof下载到FPGA中。注意在执行Programmer命令中应在Programmer/configure下的方框中打勾，然后下载。在实验台上通过模式开关选择FPGA-CPU独立调试模式010.将短路子DZ3短接且短路子DZ4断路。使FPGA-CPU所需要的时钟使用正单脉冲时钟。实验代码--实验6.6Booth乘法器LIBRARYIEEE;USEIEEE.Std_logic_1164.ALL;ENTITYbooth_multiplierISGENERIC(k:POSITIVE:=3);--inputnumberwordlengthlessonePORT(multiplicand:INBIT_VECTOR(kDOWNTO0);multiplier:INBIT_VECTOR(kDOWNTO0);clock:INBIT;product:INOUTBIT_VECTOR((2*k+2)DOWNTO0);final:OUTBIT);ENDbooth_multiplier;ARCHITECTUREstructuralOFbooth_multiplierISSIGNALmdreg:BIT_VECTOR(kDOWNTO0);SIGNALadderout:BIT_VECTOR(kDOWNTO0);SIGNALcarries:BIT_VECTOR(kDOWNTO0);SIGNALaugend:BIT_VECTOR(kDOWNTO0);SIGNALtcbuffout:BIT_VECTOR(kDOWNTO0);SIGNALadder_ovfl:BIT;SIGNALcomp:BIT;SIGNALclr_md:BIT;SIGNALload_md:BIT;SIGNALclr_pp:BIT;SIGNALload_pp:BIT;SIGNALshift_pp:BIT;SIGNALboostate:NATURALRANGE0TO2*(k+1):=0;BEGINPROCESS--mainclockedprocesscontainingallsequentialelementsBEGINWAITUNTIL(clock'EVENTANDclock='1');--registertoholdmultiplicandduringmultiplicationIFclr_md='1'THENmdreg<=(OTHERS=>'0');ELSIFload_md='1'THENmdreg<=multiplicand;ELSEmdreg<=mdreg;ENDIF;--register/shifteraccumulatespartialproductvaluesIFclr_pp='1'THENproduct<=(OTHERS=>'0');product((k+1)downto1)<=multiplier;ELSIFload_pp='1'THENproduct((2*k+2)DOWNTO(k+2))<=adderout;--addtotophalfproduct((k+1)DOWNTO0)<=product((k+1)DOWNTO0);--refreshbootmhalfELSIFshift_pp='1'THENproduct<=productSRA1;--shiftrightwithsignextendELSEproduct<=product;ENDIF;ENDPROCESS;--adderadds/subtractspartialproducttomultiplicandaugend<=product((2*k+2)DOWNTO(k+2));addgen:FORiINadderout'RANGEGENERATElsadder:IFi=0GENERATEadderout(i)<=tcbuffout(i)XORaugend(i)XORproduct(1);carries(i)<=(tcbuffout(i)ANDaugend(i))OR(tcbuffout(i)ANDproduct(1))OR(product(1)ANDaugend(i));ENDGENERATE;otheradder:IFi/=0GENERATEadderout(i)<=tcb