modulezxbo(clock0,out6,out8,out,q0,eoc,din,ale,fi,add_a,oe,out1,fs);inputclock0;//750khzinput[7:0]din;inputeoc;outputq0;output[7:0]out;output[7:0]out6,out8;//f(1)=out6=1.329khz,f(0)=out8=0.997khzoutputfs,oe,add_a,ale,out1,fi;zxbzxb0(clock0,out6,out8,out,q0);//modulationadad0(eoc,clock0,din,ale,fi,add_a,oe,out1,fs);//demodulationendmodulemodulezxb(clock0,out6,out8,out,q0);//modulationinputclock0;outputq0;//q0====dataoutput[7:0]out;output[7:0]out6,out8;reg[6:0]count;reg[7:0]out6,out8;reg[2:0]state6,state8;reg[7:0]q;reg[8:0]q1;//...[8:0]reg[2:0]q2;assignout=q[0]?out6:out8;//2--->1assignq0=q[0];assignclk=count[6];//7.978khzalways@(posedgeclock0)//count[6]====750khz/94=7.978khzif(count==93)count<=0;elsecount<=count+1;always@(posedgeclk)case(state6)3'b000:beginout6<=(8'b00010001);state6<=state6+3'b1;end3'b001:beginout6<=(8'b10000000);state6<=state6+3'b1;end3'b010:beginout6<=(8'b11101111);state6<=state6+3'b1;end3'b011:beginout6<=(8'b11101111);state6<=state6+3'b1;end3'b100:beginout6<=(8'b10000000);state6<=state6+3'b1;end3'b101:beginout6<=(8'b00010001);state6<=3'b0;enddefault:state6<=3'b0;endcasealways@(posedgeclk)case(state8)3'b000:beginout8<=(8'b00000000);state8<=state8+3'b1;end3'b001:beginout8<=(8'b00100110);state8<=state8+3'b1;end3'b010:beginout8<=(8'b10000000);state8<=state8+3'b1;end3'b011:beginout8<=(8'b11011010);state8<=state8+3'b1;end3'b100:beginout8<=(8'b11111111);state8<=state8+3'b1;end3'b101:beginout8<=(8'b11011010);state8<=state8+3'b1;end3'b110:beginout8<=(8'b10000000);state8<=state8+3'b1;end3'b111:beginout8<=(8'b00100110);state8<=3'b0;enddefault:state8<=3'b0;endcasealways@(posedgeclk)//q1====7.978khz/288=277hzbeginif(q1>=287)//288==48*6=36*8用48个周期表示out6，36个周期表示out8使长度一样q1<=0;elseq1<=q1+1;endalways@(posedgeq1[7])beginif(q2==7)q2<=0;elseq2<=q2+1;if(q2==0)q[7:0]<=8'b01001111;//测试码为01001111elsebeginq<=q>>1;endendendmodulemodulead(eoc,clock,din,ale,fi,add_a