libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;--------------------------------------------------entitylcdisport(clk:instd_logic;rst:instd_logic;lcddata:instd_logic_vector(7downto0);lcddatal:instd_logic_vector(7downto0);outadd,outaddl:inoutstd_logic_vector(8downto0);--outadd，左屏地址，outadd1，右屏地址db:outstd_logic_vector(13downto0)--位rst,e,cs1,cs2,rw,rs,db(7-0)，片选cs1为'1'，右半屏显示，cs2为'1'，左半屏显示);endlcd;--------------------------------------------------architecturebehaoflcdistypestate_typeis(pidle,idle,line_write,row_write,pline_write,prow_write,data_write,pdata_write,display,pdisplay,pline_write1,line_write1,pdata_write1,data_write1,pidle1);signalstate:state_type;signalline,line1:std_logic_vector(2downto0);---------------------------------------------------beginprocess(clk,rst)beginifrst='0'thenstate<=idle;db<="00000000000000";--清零line<="000";--line为页地址line1<="000";outadd<="000000000";--左屏地址清零outaddl<="000000000";--右屏地址清零elsif(clk'eventandclk='1')thencasestateiswhenidle=>state<=prow_write;--signaldb(13downto0)的各位rst,e,cs1,cs2,rs,rw,db(7-0)，这里的rst是液晶屏幕的rst，低电平有效whenprow_write=>state<=row_write;db<="11110001000000";--设置列地址(0-63)，设定CGRAM地址到地址计数器ACwhenrow_write=>state<=pline_write;db<="10110001000000";--列地址，e位使能，从'1'->'0'，因此状态有p和无p之分，R/W='0'，e下降沿锁存db(7downto0)whenpline_write=>state<=line_write;db<="11010010111"&line;--设置页地址(0-7)，cs1为'0'，cs2为'1'，左半屏显示，line为"000"whenline_write=>state<=pdata_write;db<="10010010111"&line;--页地址，e位使能whenpdata_write=>state<=data_write;db<="110110"&lcddata;--写入数据，lcddata为需要写入的数据，页0，列0八个点的明灭whendata_write=>state<=pidle;db<="100110"&lcddata;outadd<=outadd+1;--e位使能，左屏地址加1whenpidle=>line<=outadd(8downto6);ifoutadd(8downto0)="000000000"thenstate<=pline_write1;--写满一屏，则进入右屏elsestate<=pline_write;--循环，继续写入数据endif;-----------------------------------------------------whenpline_write1=>state<=line_write1;----右屏，设置页地址(0-7)，右屏页地址line1db<="11100010111"&lin