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LibraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;entitylfsrisgeneric(data_width:natural:=8);port(clk:instd_logic;reset:instd_logic;data_out:outUNSIGNED(data_width-1downto0));endlfsr;architecturertloflfsrissignalfeedback:std_logic;signallfsr_reg:UNSIGNED(data_width-1downto0);beginfeedback<=lfsr_reg(7)xorlfsr_reg(0);latch_it:process(clk,reset)beginif(reset='1')thenlfsr_reg<=(others=>'0');elsif(clk='1'andclk'event)thenlfsr_reg<=lfsr_reg(lfsr_reg'high-1downto0)&feedback;endif;endprocess;data_out<=lfsr_reg;endRTL;ReferenceURL:http://www.dz3w.com/eda/edasrc/6153.html