1、设计4选1多路选择器libraryieee;usestd_logic_1164.all;entitymux41isport(shuru:std_logic_vector(3downto0);xz:std_logic_vector(1downto0);shuchu:std_logic);architecturessofmun41isbeginprocess(xz)begincasexziswhen"00"=>shuchu<=shuru(0);when"01"=>shuchu<=shuru(1);when"10"=>shuchu<=shuru(2);when"11"=>shuchu<=shuru(3);whenothers=>shuchu<=null;endcase;endprocess;endss;2、设计bcd-7段led显示译码器的设计。libraryieee;useieee.std_logic_1164.all;entitybcd_7segisport(bcd_led:instd_logic_vector(3downto0);ledseg:outstd_logic_vector(6downto0));endbcd_7seg;architecturebehaviorofbcd_7segisbeginprocess(bcd_led)beginifbcd_led="0000"thenledseg<="0111111";elsifbcd_led="0001"thenledseg<="0000110";elsifbcd_led="0010"thenledseg<=“1011011”;elsifbcd_led="0011"thenledseg<="1001111";elsifbcd_led="0100"thenledseg<="1100110";elsifbcd_led="0101"thenledseg<="1101101";elsifbcd_led="0110"thenledseg<="1111101";elsifbcd_led="0111"thenledseg<="0000111";elsifbcd_led="1000"thenledseg<="1111111";elsifbcd_led="1001"thenledseg<="1101111";elseledseg<=“0000000”;endif;endprocess;endbehavior;3、在下面横线上填上合适的语句，完成下图所示rtl原理图的vhdl设计。libarryieee;useieee.std_logic_1164.all;entitymycirisport(xin,clk:instd_logic;yout:outstd_logic);endmycir;architectureoneofmycirissignala,b,c;beginb<=xinora;process(clk)beginifclk’eventandclk=‘1’thena<=c;c<=b;endif;endprocess;yout<=c;endone;4、设电路的控制端均为高电平有效，时钟端clk,电路的预置数据输入端为4位d，计数输出端也为4位q，带同步始能en、异步复位clr和预置控制ld的六进制减法计数器。libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitycnt6isport(en,clr,ld,clk:instd_logic;d:instd_logic_vector(3downto0);q:outstd_logic_vector(3downto0));endcnt6;architecturebehaofcnt6issignalqtemp:std_logic_vector(3downto0);beginprocess(clk,clr,ld)beginifclr='1'thenqtemp<="0000";--clr=1清零elsif(clk'eventandclk='1')then--判断是否上升沿ifld='1'thenqtemp<=d;--判断是否置位elsifen='1'the