四选一信号选择器：moudulemul4_1(y,s,x);input[3:0]x;input[1:0]s;outputy;regy;always@(sorx)begincase(s)2’b00:y=x[0];2’b01:y=x[1];2’b10:y=x[2];2’b11:y=x[3];default:y=1’b0;endcaseendendmodule同步复位D触发器：moduled_ff(clk,d,reset,q)；inputclk,d,reset;outputq;regq;always@(posedgeclk)beginif(reset)q<=1’b0;elseq<=d;endendmodule8位数据寄存器：modulereg8(clk,d,q);inputclk;input[7:0]d;output[7:0]q;reg[7:0]q;always@(posedgeclk)beginq<=d;endendmodule将1KHz的信号分频为50Hz：modulediv(clk_in,reset,clk_out);inputclk_in,reset;outputclk_out;reg[4:0]cnt;regclk_out;parameterdivide_period=20;//20分频always@(posedgeclk_inorposedgereset);beginif(reset)cnt<=0;elsebeginif(cnt==divide_period-1)cnt<=0;elsecnt<=cnt+1;endendalways@(posedgeclk_inorposedgereset);if(reset)clk_out<=1;elseif(cnt==dividea_period-1)clk_out<=1’b1;elseclk_out<=1’b0;endmodule十进制计数器：modulecnt(clk,clr,ena,cq,co);inputclk,clr,ena;output[3:0]cq;outputco;reg[3:0]cnt;regco;always@(posedgeclkorposedgeclr)beginif(clr)cnt<=4’b0;elseif(ena)if(cnt==4’h5)cnt<=4’h0;elsecnt<=cnt+1;endassigncq=cnt;always@(posedgeclk)beginif(cnt==4’h5)co=4’h1;elseco=4’h0;endendmodule数字秒表顶层模块：modulemiaobiao_m(clk,clr,ena,dout);inputclk,clr,ena;outputdout;wireclk,clr,ena;wire[23:0]dout;wires0,s1,s2,s3,s4,s5;clkgenu0(.clk(clk),.newclk(s0));cnt10u1(.clk(s0),.clr(clr),.ena(ena),.cq(dout[3:0]),.co(s1));cnt10u2(.clk(s1),.clr(clr),.ena(ena),.cq(dout[7:4]),.co(s2));cnt10u3(.clk(s2),.clr(clr),.ena(ena),.cq(dout[11:8]),.co(s3));cnt6u4(.clk(s3),.clr(clr),.ena(ena),.cq(dout[15:12]),.co(s4));cnt10u5(.clk(s4),.clr(clr),.ena(ena),.cq(dout[19:16]),.co(s5));cnt6u6(.clk(s5),.clr(clr),.ena(ena),.cq(dout[23:20]),.co());endmodule//通用分频器tydiv.moduletydiv(clk_in,clk_out0,clk_out1,clk_out2,clk_out3,clk_out21,clk_out32);inputclk_in;outputclk_out0,clk_out1,clk_out2,clk_out3;output[1:0]clk_out21,clk_out32;reg[7:0]cnt;//计数过程always@(posedgeclk_in)if(cnt==8’hff)cnt<=8’h00;elsecnt<=cnt+1;//分频输出assignclk_out0=cnt[