Chapter8:MainMemoryChapter8:MemoryManagementObjectivesBackgroundBaseandLimitRegistersHardwareAddressProtectionwithBaseandLimitRegistersAddressBindingBindingofInstructionsandDatatoMemoryMultistepProcessingofaUserProgramLogicalvs.PhysicalAddressSpaceMemory-ManagementUnit(MMU)DynamicrelocationusingarelocationregisterDynamicLoadingDynamicLinkingSwappingSchematicViewofSwappingContextSwitchTimeincludingSwappingContiguousAllocationHardwareSupportforRelocationandLimitRegistersContiguousAllocation(Cont.)DynamicStorage-AllocationProblemFragmentationFragmentation(Cont.)PagingAddressTranslationSchemePagingHardwarePagingModelofLogicalandPhysicalMemoryPagingExamplePaging(Cont.)FreeFramesImplementationofPageTableAssociativeMemoryPagingHardwareWithTLBEffectiveAccessTimeMemoryProtectionValid(v)orInvalid(i)BitInAPageTableSharedPagesSharedPagesExampleStructureofthePageTableHierarchicalPageTablesTwo-LevelPage-TableSchemeTwo-LevelPagingExampleAddress-TranslationScheme64-bitLogicalAddressSpaceThree-levelPagingSchemeHashedPageTablesHashedPageTableInvertedPageTableInvertedPageTableArchitectureSegmentationUser’sViewofaProgramLogicalViewofSegmentationSegmentationArchitectureSegmentationArchitecture(Cont.)SegmentationHardwareExampleofSegmentationExample:TheIntelPentiumLogicaltoPhysicalAddressTranslationinPentiumIntelPentiumSegmentationPentiumPagingArchitectureLinearAddressinLinuxThree-levelPaginginLinuxEndofChapter7