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libraryieee;useieee.std_logic_1164.all;entitydecoder_3_8isport(I_L:instd_logic_vector(2downto0);S1,S2_L,S3_L:instd_logic;F_L:outstd_logic_vector(7downto0));enddecoder_3_8;architecturedecoder_3_8pofdecoder_3_8issignalF_s:std_logic_vector(7downto0);beginprocess(I_L,S1,S2_L,S3_L)begincaseI_Liswhen"000"=>F_s<="01111111";when"001"=>F_s<="10111111";when"010"=>F_s<="11011111";when"011"=>F_s<="11101111";when"100"=>F_s<="11110111";when"101"=>F_s<="11111011";when"110"=>F_s<="11111101";when"111"=>F_s<="11111110";whenothers=>F_s<="11111111";endcase;if(S1andnotS2_LandnotS3_L)='1'thenF_L<=F_s;elseF_L<="11111111";endif;endprocess;enddecoder_3_8p;--底层16位寄存器libraryieee;useieee.std_logic_1164.all;entityregister16isport(clk,clear,cs,wr:instd_logic;d:instd_logic_vector(15downto0);q:outstd_logic_vector(15downto0));endentityregister16;architectureregisterpofregister16issignalqin:std_logic_vector(15downto0);beginprocess(clk,clear,cs,wr,qin)beginifclear='0'thenqin<="0000000000000000";elsifrising_edge(clk)thenifwr='0'andcs='0'thenqin<=d;endif;endif;ifcs='0'andwr='1'thenq<=qin;elseq<="ZZZZZZZZZZZZZZZZ";endif;endprocess;endarchitectureregisterp;libraryieee;useieee.std_logic_1164.all;entityregistergroupisport(A:instd_logic_vector(15downto0);B:outstd_logic_vector(15downto0);C:instd_logic_vector(2downto0);clk2,clear2,wr2,sta,stb,stc:instd_logic);endentityregistergroup;architecturer_groupofregistergroupissignalt:std_logic_vector(7downto0);componentdecoder_3_8port(I_L:instd_logic_vector(2downto0);S1,S2_L,S3_L:instd_logic;F_L:outstd_logic_vector(7downto0));endcomponent;componentregister16port(clk,clear,cs,wr:instd_logic;d:instd_logic_vector(15downto0);q:outstd_logic_vector(15downto0));endcomponent;beging1:decoder_3_8portmap(S1=>sta,S2_L=>stb,S3_L=>stc,I_L(0)=>C(0),I_L(1)=>C(1),I_L(2)=>C(2),F_L(0)=>t(0),F_L(1)=>t(1),
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