AFrequencyAgile40Gb/sHalfRateLinearPhaseDetectorForDataJitterMeasurementRichardKarlquist,ToddMarshall,andRoryVanTuylCraigHutchinsonAgilentTechnologiesAgilentTechnologies3500DeerCreekRd,MS25U-91400FountainGrovePkwy,MS1LSKPaloAlto,CA94304SantaRosa,CA95403richard_karlquist@agilent.comAbstract—A40Gb/shalf-ratelinearphasedetectorICforII.IMPAIRMENTSINCONVENTIONALPHASEDETECTORSNRZdata,implementedina200GHzfT,InPDHBTprocess,withanovelarchitecture,isdescribed.TheICcanbeusedforA.BasicConcepts.clockrecoveryorjittermeasurement.Thenewarchitecturehaslesscriticalinternaltiming,andbetterspeedandlinearitythanTheeasierproblemofclockjittermeasurementisausefulpreviousphasedetectors.Halfrateoperationdoublestheintroductiontodatajittermeasurement.Asimpleclockphaseallowablepropagationdelay.Dualoutputsalternateintimeanddetector(fig.3)comparestheclocktoajitter-freereferencecombinelinearly,allowingoverlapwithouterror,resultinginclock(inquadrature)usinganexclusive-ORgate.Outputgreaterlinearrange.Operationatanyrateispossiblebecausenorate-specificdelaylinesareused.Theintrinsicjitterfora40pulsesareproportionaltophase,andare½unitinterval(UI)Gb/s231-1PRBSpatternis50mUIpk-pkina320MHzlongatmidscale.Alowpassfilterintegratesthepulses.bandwidth.clockundertestaclowpassphaseIndexTerms—Datacommunication,jitter,phasedetection.filteroutreferenceclockbI.INTRODUCTIONaConventionallinearphasedetectorsforsineorsquarewavebcclocksignalscannotmeasurethephaseofNRZdata.Specialpurposelinearphasedetectors,suchastheHoggephaseFigure3.Clockjittermeasurementcircuit.detector[1],arenecessarytomeasurethephaseofNRZdataFig.4showsdatajittermeasurementbycomparingthedataandarecommonlyusedinclock/datarecovery(CDR)loopsundertest(a)tojitterfreereclockeddata(b).Again,the(fig.1)whichconvergetoanear-zerophaseerror.Linearitypulsesareproportionaltophaseand½UIatmidscale.TheawayfromzeroisnotcriticalinaCDRloop.leadingedgecoincideswithadatatransitionandthetrailingedgecoincideswithaclocktransition.Phasecan