基于FPGA的自动打铃系统的设计与实现(完整资料）(可以直接使用，可编辑优秀版资料，欢迎下载）自动打铃系统设计说明书学生姓名：罗衡学号：专业班级：电子0９-２BF报告提交日期：2０１１-11-28湖南理工学院物电学院目录一、题目及要求简介···············································1设计题目····················································12.总体要求简介················································1二、设计方案说明·················································1三、各部分功能介绍及程序·······································２1。系统框图····················································２2.选择的FPGA芯片及配置·······································23。各模块（元件)说明··········································２四、仿真结果·····················································41。计时进位····················································42。手动校时····················································5３。六点整闹铃··················································5五、说明··························································51.输入激励信号说明············································5２．输出结果说明················································6六、源程序························································61．顶层模块····················································6模式控制子模块··············································7计时及调整子模块············································8闹铃及调整子模块············································1０显示子模块··················································１1七、参考文献·····················································１４一、设计题目及要求简介１.设计题目基于FPGA的自动打铃系统的设计与实现2.总体要求简介（1)基本计时和显示功能①２4小时制显示②动态扫描显示③显示格式：８8—88－88（2)能设置当前时间（含时、分）（3）能实现基本打铃功能，上午０6:00起床铃,打铃5秒设计方案说明本系统采用自顶向下的模块化设计方法,将数字闹钟按照功能实现分为模式控制模块、计时及调整模块、闹铃及调整模块、显示模块。系统调整部分软件控制流程示意图如图２-１所示.↓开始mode↓↓12↓0校时功能↓↓闹铃功能计时功能→调整小时←→LD_hour亮调整小时turn切换切换↔↔→LD_min亮调整分钟调整分钟change↓↓LD_alert亮→返回计时返回计时图2－1各部分功能介绍及程序1。系统框图顶层电路主要由ＦPGA实现，输出信号接到八位数码管、LED指示灯及扬声器上，系统框图如图３-1所示。Altera▃AlertLD_alertLD_hourLD_minseldecodeoutclkclk_1kmodeturnchange顶层模块▶▶▶八位数码管显示模块图3—1选择的FPG