连续输入数据处理对题目的几点说明基本设计思想概述将逻辑表达式改写Y4=x1*(x2+x3+x4)+x2*(x3+x4)+x3*x4Y3=x1*(x2+x3)+x2*x3考虑使用两个数据通路同时对输入数据进行处理，最后由数据选择器选择输出结果如下图各站的描述FSM图示描述程序描述部分9个状态采用4位格雷码定义以下是FSM控制流程always@(present_stateorSerial_in)begincase(present_state)State0://initialprocessbeginSel=3'b000;if(!Serial_in)Next_state=State0;elseNext_state=State1;//statejumpendState1:beginif(!Serial_in)Next_state=StateY;elseNext_state=State2;endState2:beginif(!Serial_in)Next_state=StateY;elseNext_state=State3;endState3:beginif(!Serial_in)Next_state=StateY3;elseNext_state=State4;endState4:beginif(!Serial_in)Next_state=StateY4;elseNext_state=State5;endState5:beginif(!Serial_in)Next_state=StateY;elseNext_state=State5;endStateY://outputprocessbeginSel=3'b100;Next_state=State0;endStateY3:beginSel=3'b010;Next_state=State0;endStateY4:beginSel=3'b001;Next_state=State0;enddefault:Next_state=State0;endcaseend数据通路代码always@(posedgeclk)beginif(!Rst)beginZ0<=8'b0;Z4<=14'b0;Z5<=19'b0;Z6<=11'b0;present_state<=State0;//statejumpendelsebeginif(!Start)beginZ0<=8'b0;Z4<=14'b0;Z5<=19'b0;Z6<=11'b0;present_state<=State0;end//Start=0thenjumptostateelseZ0<=Serial_in;Z4<=Z3;Z5<=Z2;Z6<=Z1;//innerregisterrelationpresent_state<=Next_state;endend内部寄存器之间关系代码always@(Z0orZ4orZ5orZ6orRstorStart)//dataprocessbeginif((!Rst)||(!Start))beginZ1<=10'b0;Z2<=18'b0;Z3<=13'b0;endelseZ1<=Z0+Z6;Z2<=Z0*Z6+Z5;Z3<=Z0[7:4]*Z0[3:0]+Z4;end结果输出代码always@(SelorZ0orZ4orZ5orZ6)//outputselectioncase(Sel)3'b000:beginY<=14'bz;Y3<=19'bz;Y4<=18'bz;Done<=1'b0;end3'b100:beginY<=Z4;Y3<=19'bz;Y4<=18'bz;Done<=1'b1;end3'b010:beginY<=14'bz;Y3<=Z5;Y4<=18'bz;Done<=1'b1;end3'b001:beginY<=14'bz;Y3<=19'bz;Y4<=Z5[17:0];Done<=1'b1;enddefault:beginY<=14'bz;Y3<=19'bz;Y4<=18'bz;Done<=1'b0;endendcaseTestbanch部分测试码逻辑仿真波形比较Serial_in=8'b0001_0010;Serial_in=8'b0010_0011;Serial_in=8'b0010_0100;Serial_in=8'b0100_0111;Serial_in=8'b0110_0101;Serial_in=8'b0000_0000;