集成电路设计IntigratedCircuitDesign李德识TEL：68774465dsli@whu.edu.cnResearchInterestsIntelligentSystem/EmbeddedSystemSoCDesign&VerificationAdhocNetworks，WirelessSensorNetworks，MeshNetworksSignalDetecting&Processing参考书课程来源实验室建设&科学研究课程内容课程内容（续）课程名称及关系课程目标学习方法成绩考核EDA实验使用的环境及工具1-1集成电路发展信息传输的变迁IC’skeyAdvantagesICtoSystemTheFirstComputerIBMFirstAutomaticCalculator(HarvardUniversity)ENIAC-Thefirstelectroniccomputer(1946，用于大炮发射表计算)TheTransistorRevolutionTransistorRevolutionTheFirstIntegratedCircuitsTransistorsMOSFETTechnology1-2摩尔定律（Moore’sLaw）TransistorCountsMoore’slawinMicroprocessorsDRAMChipCapacityIntel4004Micro-ProcessorIntelPentium(IV)microprocessor芯片尺寸/面积（DieSize）FrequencyPowerwillbeamajorproblemPowerdensity速度、面积、功耗是IC设计主要约束条件（多优化目标）。TechnologyDirections:SIA（美国半导体协会）RoadmapSourceMcCleanreport2009BrochureSource:McCleanreport2009BrochureSource:McCleanreport2009BrochureCellPhoneSoCExample:NetworkChip1-3IC分类按工艺分类按实现方式分类按用途分类1-4产业（SemiconductorRelatedIndustry）芯片代工厂（chipfoundryindustry)2009Top2049ICInsight2010broch1-5设计挑战（DesignChallenges）1-6层次化设计设计鸿沟层次化设计---动因抽象(Abstraction)设计抽象层次（DesignAbstractionLevels）问题Dealingwithcomplexity设计方法例：ComponentHierarchyAhierarchicallogicdesign例:RefinementsofelectronicdesignDesignabstractions例：Layoutanditsabstractions棍棒图StickdiagramTransistorschematicMixedschematicCircuitabstractionDigitalabstraction寄存器传输器级（Register-Transfer-Level）抽象1-7设计流程DesignProcessTypicalDesignFlow-IndustryHowtoDesignanASICHDL-basedDesignFlow设计说明设计规划DesignPlanning综合（Synthesis）LogicSynthesisEstimatedTiming布图规划Floorplanning布局PlacementRoutingPlaceandRouteLayoutDesign:P&RvsFullCustom静态时间分析（Statictiminganalyzer）calculatespoint-to-pointtimingforsynchronouscircuits:建起与保持时间（setupandholdtime）错误关键路径（criticalpath）分析…延迟时间计算依据interconnection:input/outputload.gateintrinsic:readfromlibrarymodel.globalenvironment:temperature,voltageandprocessde-ratings.PowerSupplySynthesisClockTreeSynthesisPhysicalCellLayoutActualPhysicalTimingPhysicalVerification1-8设计要求本章要点