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libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityfenpinisPort(RESET:instd_logic;CLK:instd_logic;CLKOUT1:outstd_logicCLKOUT1:outstd_logicCLKOUT1:outstd_logic);--分配三个输出口endfenpin;architectureBehavioraloffenpinissignaldiv_val1:integerrange0to2;--分频值＝2*2signaldiv_val2:integerrange0to4;signaldiv_val3:integerrange0to8;signaldiv_clk1:std_logic;--因为CLKOUT是out类型，--用div_clk1来暂存signaldiv_clk2:std_logic;signaldiv_clk3:std_logic;beginprocess(CLK,RESET)beginif(RESET='0')then--RESET的优先级最高div_clk1<='0';div_clk2<='0';div_clk3<='0';elsif(CLK'eventandCLK='1')then--判断CLK上升沿if(div_val1=2)thendiv_val1<=0;div_clk1<=notdiv_clk1;elsediv_val1<=div_val1+1;--在CLK的上升--沿div_val1自加1，加到2时清零并将div_clk1取反endif;if(div_val2=4)thendiv_val2<=0;div_clk2<=notdiv_clk2;elsediv_val2<=div_val2+1;--在CLK的上升--沿div_val2自加1，加到4时清零并将div_clk2取反endif;if(div_val3=8)thendiv_val3<=0;div_clk3<=notdiv_clk3;elsediv_val3<=div_val3+1;--在CLK的上升--沿div_val3自加1，加到8时清零并将div_clk3取反endif;endif;endprocess;CLKOUT1<=div_clk1;CLKOUT2<=div_clk2;CLKOUT3<=div_clk3;endBehavioral;
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