Verilog编写的CIC代码//internalclk>=8*outputclkmodulecicmodule(inputclk,internalclk,outputclk,preset,datainput,dataoutput);parameterDataWidth=18;parameterOutputDiv=4;//OutputDiv=(order-1)*ln(outputclk/inputclk)/ln(2)inputinputclk;inputinternalclk;inputoutputclk;inputpreset;inputsigned[(DataWidth-1):0]datainput;outputsigned[(DataWidth-1):0]dataoutput;//registersreginputclkperiod;reg[2:0]statecount;regsigned[(DataWidth-1):0]inputreg;//--stage1(comb)signals,gain=2->+1bitregsigned[DataWidth:0]int0;//--stage2(comb)signals,gain=2->+1bitregsigned[DataWidth+1:0]int1;//--stage3(comb)signals,gain=2->+1bitregsigned[DataWidth+2:0]int2;regsigned[DataWidth+2:0]tempreg0;regsigned[DataWidth+2:0]tempreg1;//--stage4(integrator)signals,gain=2->+1bitregsigned[DataWidth+4:0]int3;//--stage5(integrator)signals,gain=0.5->-1bitregsigned[DataWidth+5:0]int4;//--stage6(integrator)signals,gain=4->+2bitregsigned[DataWidth+7:0]int5;regsigned[DataWidth+7:0]addInputA;regsigned[DataWidth+7:0]addInputB;regsigned[DataWidth+7:0]addInputBsig;regaddsubSelect;wiresigned[DataWidth+7:0]addOutput;//Add/sunalways@(addInputBoraddsubSelect)beginif(addsubSelect)addInputBsig=-addInputB;elseaddInputBsig=addInputB;end//AddassignaddOutput=addInputA+addInputBsig;//Outputassignassigndataoutput=int5>>>OutputDiv;//Clkoperationsalways@(posedgeinputclkorposedgeoutputclkorposedgepreset)beginif(preset==1)inputclkperiod=1;elseif(inputclk==1)inputclkperiod=1;elseinputclkperiod=0;endalways@(posedgeinputclkorposedgepreset)beginif(preset==1'b1)inputreg=0;elseinputreg=datainput;endalways@(posedgeinternalclkorposedgeinputclkorposedgepreset)beginif(preset==1)statecount=0;elseif(inputclk==1)statecount=0;elsestatecount=statecount+1;endalways@(negedgeinternalclkorposedgepreset)beginif(preset==1)begintempreg0=0;tempreg1=0;int0=0;int1=0;int2=0;int3=0;int4=0;int5=0;endelsebegincase(statecount)3'd0:beginif(inputclkperiod==1)begintempreg0=