4路E1反向复用FPGA设计方案第页共NUMPAGES55页4路E1反向复用FPGA设计方案目录1TOC\o"1-3"\h\zHYPERLINK\l"_Toc218222432"4路E1反向复用FPGA设计方案PAGEREF_Toc218222432\h5HYPERLINK\l"_Toc218222433"1系统工作特点PAGEREF_Toc218222433\h5HYPERLINK\l"_Toc218222434"2检测和建链、拆链PAGEREF_Toc218222434\h5HYPERLINK\l"_Toc218222435"2.1寄存器定义PAGEREF_Toc218222435\h5HYPERLINK\l"_Toc218222436"2.2检测和建链过程：PAGEREF_Toc218222436\h7HYPERLINK\l"_Toc218222437"2.3拆链、重新建链和带宽自动调整PAGEREF_Toc218222437\h10HYPERLINK\l"_Toc218222438"2.4信令定义PAGEREF_Toc218222438\h11HYPERLINK\l"_Toc218222439"2.5复帧和宏帧PAGEREF_Toc218222439\h12HYPERLINK\l"_Toc218222440"2.5.1复帧的收发与同步PAGEREF_Toc218222440\h12HYPERLINK\l"_Toc218222441"2.5.2宏帧的收发与同步PAGEREF_Toc218222441\h13HYPERLINK\l"_Toc218222442"3发送模块和接受模块工作流程PAGEREF_Toc218222442\h15HYPERLINK\l"_Toc218222443"4系统组成功能框图PAGEREF_Toc218222443\h20HYPERLINK\l"_Toc218222444"5CPU接口PAGEREF_Toc218222444\h21HYPERLINK\l"_Toc218222445"5.1功能PAGEREF_Toc218222445\h21HYPERLINK\l"_Toc218222446"5.2寄存器PAGEREF_Toc218222446\h21HYPERLINK\l"_Toc218222447"5.2.1配置寄存器(REG_CONFIG)PAGEREF_Toc218222447\h22HYPERLINK\l"_Toc218222448"5.2.2状态寄存器PAGEREF_Toc218222448\h23HYPERLINK\l"_Toc218222449"5.3CPU模块功能框图PAGEREF_Toc218222449\h30HYPERLINK\l"_Toc218222450"5.4CPU接口工作特点PAGEREF_Toc218222450\h31HYPERLINK\l"_Toc218222451"5.4.1CPU中断响应PAGEREF_Toc218222451\h31HYPERLINK\l"_Toc218222452"5.4.2CPU对芯片复位PAGEREF_Toc218222452\h31HYPERLINK\l"_Toc218222453"6各模块接口信号PAGEREF_Toc218222453\h32HYPERLINK\l"_Toc218222454"6.1IM发送模块接口信号PAGEREF_Toc218222454\h32HYPERLINK\l"_Toc218222455"6.2信令插入和4E1成帧模块接口信号PAGEREF_Toc218222455\h34HYPERLINK\l"_Toc218222456"6.3HDB3编码模块接口信号PAGEREF_Toc218222456\h36HYPERLINK\l"_Toc218222457"6.4E1环回处理模块接口信号PAGEREF_Toc218222457\h37HYPERLINK\l"_Toc218222458"6.5HDB3解码模块接口信号PAGEREF_Toc218222458\h38HYPERLINK\