数字时钟设计-本章概要数字时钟设计-数字时钟的功能要求数字时钟设计-数字时钟的结构数字时钟设计-数字时钟的结构数字时钟设计-控制模块结构数字时钟设计-控制模块结构数字时钟设计-控制模块结构数字时钟设计-控制模块结构数字时钟设计-控制模块结构数字时钟设计-控制模块结构数字时钟设计-控制模块结构数字时钟设计-控制模块结构数字时钟设计-控制模块结构数字时钟设计-控制模块结构数字时钟设计-控制模块结构数字时钟设计-主程序--信号定义：architectureBehavioralofclockissignalsec_counter1:std_logic_vector(3downto0);signalsec_counter2:std_logic_vector(3downto0);signalmin_counter1:std_logic_vector(3downto0);signalmin_counter2:std_logic_vector(3downto0);signalhour_counter1:std_logic_vector(3downto0);signalhour_counter2:std_logic_vector(3downto0);signaldivcounter:std_logic_vector(3downto0);signaldiv_clk:std_logic;signalscancounter:std_logic_vector(1downto0);signalscan_clk:std_logic;signalscan_out:std_logic_vector(2downto0);signalsecseg1,secseg2,minseg1,minseg2,hourseg1,hourseg2:std_logic_vector(7downto0);begin--计数时钟，对外部输入时钟分频，此处只适用于仿真，实际进行时间计数时，分频后时钟应该满足1HZ。process(rst,clk)beginif(rst='0')thendivcounter<="0000";div_clk<='0';elsif(rising_edge(clk))thenif(divcounter="1111")thendivcounter<="0000";div_clk<=notdiv_clk;elsedivcounter<=divcounter+'1';endif;endif;endprocess;--仿真时数码管扫描时钟，实际中需根据具体情况进行调解时钟频率process(rst,clk)beginif(rst='0')thenscancounter<="00";scan_clk<='0';elsif(rising_edge(clk))thenif(scancounter="11")thenscancounter<="00";scan_clk<=notscan_clk;elsescancounter<=scancounter+'1';endif;endif;endprocess;--时钟计数部分主进程--时钟复位clock:process(div_clk,rst)beginif(rst='0')thensec_counter1<=X"0";sec_counter2<=X"0";min_counter1<=X"0";min_counter2<=X"0";hour_counter1<=X"0";hour_counter2<=X"0";--手动调分，递增elsif(rising_edge(div_clk))thenif(inc_min='0')thenif(min_counter1=X"9")thenmin_counter1<=X"0";if(min_counter2>=X"5")thenmin_counter2<=X"0";elsemin_counter2<=min_counter2+1;endif;elsemin_counter1<=min_counter1+1;endif;--手动调分，递减elsif(sub_min='0')thenif(min_counter1=X"0")thenmin_counter1<=X"9";if(min_counter2=X"0")thenmin_counter2<=X"5";elsemin_counter2<=min_counter2-1;endif;else