6.1基于VHDL的HDB3码程序设计插”B”模块的实现count1<=0;endif;endif;elsif(codeoutv=“01”)thencount1<=count1+1;s1(4)<=s1(3);s0(4)<=s0(3);elses1(4)<=s1(3);s0(4)<=s0(3);count1<=count1;endif;endif;endprocessadd_b;codeoutb<=s1(4)&s0(4);单极性变双极性的实现编码器模块的总程序signals1:std_logic_vector(4downto0):=“00000”;signalclkb:std_logic;signals3:std_logic_vector(1downto0);signalflag1b:integerrange1downto0;signalflagv:integerrange1downto0;signalfirstv:integerrange0to1;componentdffport(d:instd_logic;clk:instd_logic;q:outstd_logic);endcomponent;beginadd_v:process(clk,clr)beginif(rising_edge(clk))thenif(clr=‘1’)thencodeoutv<=“00”;count<=0;elsecasecodeiniswhen‘1’=>codeoutv<=“01”;count0<=0;when‘0’=>if(count0=3)thencodeoutv<=“11”;count0<=0;elsecount0<=count0+1;codeoutv=“00”;endif;whenothers=>codeoutv<=“00”;count0<=count0;endcase;endif;endif;endprocessadd_v;s0(0)<=codeoutv(0);s1(0)<=codeoutv(1);ds11:dffportmap(s1(0),clk,s1(1));ds01:dffportmap(s0(0),clk,s0(1));ds12:dffportmap(s1(1),clk,s1(2));ds02:dffportmap(s0(1),clk,s1(2));ds13:dffportmap(s1(2),clk,s1(3));ds03:dffportmap(s0(2),clk,s1(3));-ds14:dffportmap(s1(3),clk,s1(4));-ds04:dffportmap(s0(3),clk,s0(4));-ds15:dffportmap(s1(4),clk,s1(5));-ds05:dffportmap(s0(4),clk,s0(5));bclk:clkb<=notclk;add_b:process(clkb)beginif(rising_edge(clkb))thenif(codeoutv=“11”)thenif(firstv=0)thencount1<=0;firstv<=1;s1(4)<=s1(3);s0(4)<=s0(3);elseif(count1=0)thens1(4)<=‘1’;s0(4)<=‘0’;count1<=0;elses1(4)<=s1(3);s0(4)<=s0(3);count1<=0;endif;endif;elsif(codeoutv=“01”)thencount1<=count1+1;s1(4)<=s1(3);s0(4)<=s0(3);elses1(4)<=s1(3);s0(4)<=s0(3);count1<=count1;endif;endif;endprocessadd_b;codeoutb<=s1(4)&s0(4);output:process(clk)beginif(rising_edge(clk))thenif((codeoutb=“01”)or(codeoutb=“10”))thenif(flag1b=1)thencodeout<=“01”;flag1b<=0;elsecodeout<=“11”;flag1b<=1;endif:elsif(codeoutb=“11”)thenif(flag1b=1)thencodeout<=“11”;elsecodeout<=“01”;endif;elsecodeout<=“00”;flag1b<=flag1b